1. Field of the Invention
The present invention relates to a data transfer system and a readjustment control method for use with the system, and more particularly to readjusting the sampling timing for a DLL (Delay Locked Loop) circuit.
2. Description of the Prior Art
In recent years, a DLL circuit has been incorporated for maintaining synchronization of data. Conventionally, if an input signal was taken in at a false timing before the phase adjustment of the DLL circuit at the time of turning on the power or returning from the power down operation, the internal circuits possibly might cause a malfunction.
A method for solving this problem has been proposed in which in an integrated circuit device having a self timing control circuit for generating an input take-in timing signal in phase adjustment with the internal clock, during the period of phase adjustment of the self timing control circuit, input signals such as a command input signal, an address input signal, a data input signal and the like, supplied externally to an input circuit, are inhibited from being taken into the inside (e.g., refer to Japanese Patent Laid-Open No. 2000-163963).
In this case, when the phase adjustment of the self timing control circuit is ended to some extent, the operation of taking in the input signals using an input take-in timing signal in the input circuit are permitted. To perform this operation, the input circuit generates an input take-in control signal, employing a lock-on signal, an adjust signal or an input stop signal for the DLL circuit, for example.